FPGA Controller Based Experimental Analysis of A Cascaded Hybrid Bridge Seven Level Inverter

Parul Gaur
Page No: 16-21
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In today’s era, reliable and good quality power is an essential requirement in industry, which can be supplied by inverters at medium and high power. Most of the appliances in the industry require high power or medium power for their operation. Power electronics devices such as inverters work on medium voltage and high power and are suitable for industrial applications. Multilevel inverters are more superior to conventional inverters because of lower harmonics and switching losses, but as the number of levels increases, complexity also increases. Therefore, maintaining the harmonics at lower level and lesser complexity of multilevel inverters is a challenge for researchers. In this research paper, a novel approach for implementation of seven level cascaded hybrid bridge configuration of multilevel inverter using direct current source and photovoltaic panels is being used. The basic working principle of seven level cascaded hybrid bridge inverter, pulse width modulation techniques and total harmonic distortion are explained through simulations in Matlab and Xilinx 14.3 software and the same is experimentally validated through FPGA controller based Spartan 6. The designed seven level inverter results in lower total harmonic distortion with lesser complexity as the number of switching devices is thirty six only. The designed seven level inverter can be further used in reactive power compensation devices such as static synchronous compensator for better control of active and reactive power.

Citations

APA: Parul Gaur (2025). FPGA Controller Based Experimental Analysis of A Cascaded Hybrid Bridge Seven Level Inverter. DOI: 10.86493/OTJ.25341004

AMA: Parul Gaur. FPGA Controller Based Experimental Analysis of A Cascaded Hybrid Bridge Seven Level Inverter. 2025. DOI: 10.86493/OTJ.25341004

Chicago: Parul Gaur. "FPGA Controller Based Experimental Analysis of A Cascaded Hybrid Bridge Seven Level Inverter." Published 2025. DOI: 10.86493/OTJ.25341004

IEEE: Parul Gaur, "FPGA Controller Based Experimental Analysis of A Cascaded Hybrid Bridge Seven Level Inverter," 2025, DOI: 10.86493/OTJ.25341004

ISNAD: Parul Gaur. "FPGA Controller Based Experimental Analysis of A Cascaded Hybrid Bridge Seven Level Inverter." DOI: 10.86493/OTJ.25341004

MLA: Parul Gaur. "FPGA Controller Based Experimental Analysis of A Cascaded Hybrid Bridge Seven Level Inverter." 2025, DOI: 10.86493/OTJ.25341004